1. Field of the Invention
The present invention relates to computing systems, and more particularly, to efficiently processing direct memory access (“DMA”) operations.
2. Background of the Invention
Computing systems typically include several functional components. These components may include a central processing unit (CPU), main memory, input/output (“I/O”) devices, and streaming storage devices (for example, tape drives). In conventional systems, the main memory is coupled to the CPU via a system bus or a local memory bus. The main memory is used to provide the CPU access to data and/or program information that is stored in main memory at execution time. Typically, the main memory is composed of random access memory (RAM) circuits. A computer system with the CPU and main memory is often referred to as a host system.
Host systems often communicate with peripheral devices via an interface such as the Peripheral Component Interconnect (“PCI”) interface, a local bus standard using parallel data transfer that was developed by Intel Corporation®. The PCI standard is incorporated herein by reference in its entirety.
PCI-X is another bus standard that is compatible with existing PCI cards using the PCI bus. PCI-X improves the data transfer rate of PCI from 528 MBps to as much as 1 GBps. The PCI-X standard (incorporated herein by reference in its entirety) was developed by IBM®, Hewlett Packard Corporation® and Compaq Corporation® to increase performance of high bandwidth devices, such as Gigabit Ethernet standard and Fibre Channel Standard based devices.
More recently, PCI-Express, a standard interface incorporating PCI transaction protocols at the logical level, but using serial data transfer at the physical level has been developed to offer better performance than both the PCI or PCI-X standards. PCI-Express is an Input/Output (“I/O”) bus standard (incorporated herein by reference in its entirety) that uses discrete logical layers to process inbound and outbound information.
Various other standard interfaces are also used to move data between host systems and peripheral devices. Fibre Channel is one such standard. Fibre Channel (incorporated herein by reference in its entirety) is an American National Standard Institute (ANSI) set of standards, which provides a serial transmission protocol for storage and network protocols.
Host systems are used in various network applications, including storage area networks (“SANs”). In SANs, plural memory storage devices are made available to various host computing systems. Data in a SAN is typically moved between plural host systems and storage systems (or storage devices, used interchangeably throughout this specification) through various controllers/adapters, for example, host bus adapters (“HBAs”).
HBAs (a PCI/PCI-X/PCI-Express device) that are placed in SANs receive serial data streams (bit stream), align the serial data and then convert it into parallel data for processing. HBAs operate as a transmitting device as well as a receiving device.
DMA modules are used by HBAs to perform data transfers between host memory and storage devices without intervention from the host CPU. DMA modules provide address and control information to generate read and write accesses to host memory.
A DMA read request is a request from a DMA module (or channel) to transfer data from a host system to a storage device. A DMA write request is a request from a DMA module to transfer data from the storage device to a host system.
HBAs typically implement multiple DMA channels with an arbitration module that arbitrates for the access to a PCI/PCI-X bus or PCI-Express link. This allows an HBA to switch contexts between command, status and data. Multiple channels are serviced in periodic bursts.
A single DMA channel also typically breaks up large DMA data transfer request into smaller ones to comply with interface protocol requirements. Some of the factors affecting the break up of DMA request include payload size requirement and address boundary alignment on PCI-X/PCI-Express interface, and frame size negotiation on fibre channel interface and others.
The PCI-Express architecture, by design, treats DMA read request and resulting data return (transaction layer packet called Completion) as two separate transactions due to independent unidirectional transmit and receive links. The standard architecture has latency problems in completing read requests.
If a DMA channel breaks up read request for a large data transfer into multiple read requests of smaller sizes, the sequential nature of read requests coupled with access latencies in the host memory controller can considerably reduce the read data transfer throughput.
FIG. 1C illustrates the latency problem in PCI-X and/or PCI-Express systems (used interchangeably through out this specification). A first read request is received at time T0. The data for this request is received at time T1. Thereafter, a second read request from the same DMA channel is received at time T2 (after “Completion Transaction” for first read request is received at time T1) and data for that request is received at time T3. The latency is cumulative and reduces the overall efficiency of data transfer from a host system to the Fibre Channel network, via a HBA.
Therefore, there is a need for a method and system that can efficiently process read requests in PCI-X/PCI-Express host bus adapters and other similar devices.